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-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:56:32 12/02/2009 
-- Design Name: 
-- Module Name:    Mux - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Mux is
    Port ( Input1 : in  STD_LOGIC_VECTOR (15 downto 0);
           Input2 : in  STD_LOGIC_VECTOR (15 downto 0);
           Input3 : in  STD_LOGIC_VECTOR (15 downto 0);
           Input4 : in  STD_LOGIC_VECTOR (15 downto 0);
           Control : in  STD_LOGIC_VECTOR (1 downto 0);
           Output : out  STD_LOGIC_VECTOR (15 downto 0));
end Mux;

architecture FourTo1Mux_16bit of Mux is
begin
		with Control select
			Output <= Input1 when "00",
						 Input2 when "01",
						 Input3 when "10",
						 Input4 when "11",
						 "0000000000000000" when others;
end FourTo1Mux_16bit;


library IEEE;
use IEEE.std_logic_1164.all;

package mips_mux is
	component Mux
		Port ( Input1 : in  STD_LOGIC_VECTOR (15 downto 0);
				 Input2 : in  STD_LOGIC_VECTOR (15 downto 0);
				 Input3 : in  STD_LOGIC_VECTOR (15 downto 0);
				 Input4 : in  STD_LOGIC_VECTOR (15 downto 0);
             Control : in  STD_LOGIC_VECTOR (1 downto 0);
             Output : out  STD_LOGIC_VECTOR (15 downto 0));
	end component;
end mips_mux;